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NXP Semiconductors /LPC408x_7x /SYSCON /CLKSRCSEL

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Interpret as CLKSRCSEL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SELECTS_THE_INTERNAL)CLKSRC 0RESERVED

CLKSRC=SELECTS_THE_INTERNAL

Description

Clock Source Select Register

Fields

CLKSRC

Selects the clock source for sysclk and PLL0 as follows:

0 (SELECTS_THE_INTERNAL): Selects the Internal RC oscillator as the sysclk and PLL0 clock source (default).

1 (SELECTS_THE_MAIN_OSC): Selects the main oscillator as the sysclk and PLL0 clock source.
RESERVED

Reserved. Read value is undefined, only zero should be written.

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data